SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

You may be comfortable with procedural code, but writing constraints and understanding random distributions requires a new way of thinking. Here are some issues you may encounter when trying to create random stimulus.
When creating a testbench, you may be tempted to use the int, byte, or other signed types for counters and other simple variables. Don't use them in random constraints unless you really want signed values. What values are produced when the class in Example 6-32 is randomized? It has two random variables and wants to make the sum of them 64.
class SignedVars; rand byte pkt1_len, pk2_len; constraint total_len { pkt1_len + pk2_len == 64; }endclass Obviously, you could get pairs of values such as (32, 32) and (2, 62). But you could also see (-64, 128), as this is a legitimate solution of the equation, even though it may not be what you wanted. To avoid meaningless values such as negative lengths, use only unsigned random variables.
class Vars32; rand logic [31:0] pkt1_len, pk2_len; // unsigned type constraint total_len { pkt1_len + pk2_len == 64; }endclass<span class="beginpage"> pagenum="165"><a name="645"></a><a name="IDX-165"></a></span> Even this version causes problems, as large values of pkt1_len and pkt2_len, such as 32 'h80000040 and 32'h80000000, wrap around when added together and...