SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

6.7: Valid Constraints

6.7 Valid Constraints

A good randomization technique is to create several constraints to ensure the correctness of your random stimulus, known as "valid constraints." For example, a bus read-modify-write command might only be allowed for a longword data length.

Example 6-22: Checking write length with a valid constraint
class BusTrans;  rand enum {BYTE, WORD, LWRD, QWRD} length;  rand enum {READ, WRITE, RMW, INTR} opc;  constraint valid_RMW_LWRD {   (opc == RMW)  -> length == LWRD;  }endclass

Now you know the bus transaction obeys the rule. Later, if you want to violate the rule, use constraint_mode to turn off this one constraint. You should have a naming convention to make these constraints stand out, such as using the prefix valid as shown above.

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