SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

A good randomization technique is to create several constraints to ensure the correctness of your random stimulus, known as "valid constraints." For example, a bus read-modify-write command might only be allowed for a longword data length.
class BusTrans; rand enum {BYTE, WORD, LWRD, QWRD} length; rand enum {READ, WRITE, RMW, INTR} opc; constraint valid_RMW_LWRD { (opc == RMW) -> length == LWRD; }endclass Now you know the bus transaction obeys the rule. Later, if you want to violate the rule, use constraint_mode to turn off this one constraint. You should have a naming convention to make these constraints stand out, such as using the prefix valid as shown above.