Overview

This chapter focuses on parallel programming for network-on-chip (NoC) platforms, with a significant number of cores operating in parallel. Raising the abstraction level for computation and communication specification seems the only way to master the complexity of mapping a large software application onto an multi-processor systems-on-chip (MPSoC). Even though the bulk of this book is on architectural and lower-level issues, high-level programming models are needed to support abstraction of hardware and software architectures.

Parallel computer architectures and parallel programming have deep roots in high-performance computing. Early programming abstractions for parallel machines go back almost 60 years. In the last half-century, the traditional dichotomy between shared memory and message passing as programming models for multi-processor systems has consolidated. For small-to-medium scale multi-processor systems consensus was reached on cache-coherent architectures based on shared memory programming model. In contrast, large-scale high-performance multi-processor systems have converged toward non-uniform memory access (NUMA) architectures based on message passing (MP) [5, 6]. As already discussed in previous chapters, several characteristics differentiate NoCs and MPSoCs from classical multiprocessing platforms, and this view must be carefully revisited.

First, the "on-chip" nature of interconnects reduces the cost of interprocessor communication. The cost of delivering a message on an on-chip network is in fact at least one order of magnitude lower (powerand performance-wise) than that of an off-chip interconnect. NoC platforms feature a growing amount of on-chip memory and the cost of on-chip memory accesses is also smaller with respect to off-chip memories. Second, NoCs are often deployed...