TABLE OF CONTENTS The continued scaling in process technologies makes it imperative to consider reliability as a cross-cutting problem concerning not only test engineers but also system designers. In the network-on-chips (NoC) domain, the task to guarantee reliable data transfers across inherently unreliable physical links is performed by the data-link layer. In this context, communication reliability will be strongly impacted by the reliability of switch-to-switch connections. The main challenge is represented by the increased prominence of noise sources with shrinking feature sizes. Lower supply voltages, smaller nodal capacitances, a decrease of inter-wire spacing, the increasing role of coupling capacitance, the higher clock frequencies will make NoC communication increasingly sensitive to both internal (power supply noise, crosstalk noise, inter-symbol inter-ference) and external ( electromagnetic interference (EMI), thermal noise, noise induced by alpha particles) noise sources.
Traditional fault models are not proving capable of capturing the characteristics and the effects of failure mechanisms affecting on-chip communication links. Disturbances will in fact concern multiple adjacent wires, so that errors on these wires can no longer be considered as sta-tistically independent, as is the case for many noise models traditionally used to assess performance and error resilience of on-chip communication schemes. Moreover, errors will be inherently bidirectional, thus exceeding the detection capability of traditional error control techniques such as the Berger code.
Common practices to enhance communication reliability include the insertion of repeaters, shielding of link wires, proper global wire configu-rations, spacing rules, error control coding-aware layout modifications, or unbalancing of link line drivers.
