TABLE OF CONTENTS The AMBA AXI protocol family defines a new set of on-chip interface protocols for SoC designs, and is interoperable with existing bus technology defined in the AMBA 2 specification. The AXI protocol is an advanced microprocessor system bus interface which aims at meeting the interface requirements of a wide range of components and targets low-latency and high-bandwidth designs.
The distinctive features of the AXI protocol include [58]:
Separate address/control and data phases.
Support for unaligned data transfers using byte strobes.
Burst-based transactions with only start address issued.
Separate read and write data channels to enable low-cost direct memory access (DMA).
Ability to issue multiple outstanding addresses.
Out-of-order transaction completion.
Easy addition of register stages to provide timing closure.
Protocol includes optional extensions that cover signaling for lowpower operation.
In practice, the combination of these features brings the following advantages to system interconnects based on AMBA AXI:
Independently acknowledged address and data channels.
Out-of-order completion of bursts.
Exclusive access (atomic transaction).
System-level cache support.
Access security support.
Unaligned address and byte strobe.
Static burst, which allows bursts to FIFO memories.
Low-power mode.
The AXI protocol is burst based. Bursts are managed in quite a different way with respect to AMBA AHB. For instance, address information can be issued ahead of the actual data transfer. Combining this feature with the multiple outstanding transaction support and the out-of-order completion option, we can get the waveform behavior of Fig. 6.4, where the enhanced flexibility of AXI...
