TABLE OF CONTENTS Designing networks on chips (NoCs) is a complex process and spans several abstraction levels, ranging from the transaction to the physical levels. Design choices are difficult to make, because most figures of merit of the network depend highly on high-level decisions on architectures and protocols. Yet these decisions can only be validated while considering physical layer measures, such as delays on interconnection links. Thus, potential design closure issues may require designers to explore various configurations with different parameters in the search for those that satisfy the network and overall system specifications. Computer-aided design (CAD) tools are therefore very useful to shorten the design time and provide design closure.
The major steps involved in designing NoCs include the following:
Analyzing and characterizing application traffic.
Synthesizing the NoC topology for the application.
Mapping and binding of the cores with the NoC components.
Finding paths for the traffic flows and reserving resources across the NoC.
Determining NoC architectural parameters, such as the data width of the links, buffer sizes, and frequency of operation.
Verifying the designed NoC for correctness and performance.
In order to achieve efficient NoC designs, many of these steps are performed together. As an example, mapping components and selecting paths for the different traffic flows can be done jointly during topology synthesis. To achieve design closure, it is important to automate and integrate the different design steps. Thus, the different design phases are coupled by providing information feedback. For example, if simulation shows that performance targets are...
