TABLE OF CONTENTS Recently a new trend of processor architecture for SoC design has emerged: customizable processors [47]. These processor cores are highly configurable (e.g., registers and memories) and allow SoC system designers to define new instructions and registers to match target application performance requirements. Usually, the customization process is tool assisted. For instance, the Tensilica's Xtensa processor extension synthesis compiler (XPRES [46]) uses three techniques to create optimized Xtensa processor configurations: operator fusion, multiple data (SIMD) vectorization, and flexible-length instruction extensions (FLIX) [47].
At the same time, the need to provide high-performance computation is pushing the development of multiprocessing architectures based on the instantiation of multiple customizable processor cores and hardware accelerators. Therefore, high-bandwidth inter-processor communication is becoming a critical issue for state-of-the-art SoCs. In order to overcome the traditional bus bottleneck, designers of configurable cores are introducing multiport access to the processor's internal execution units. This trend is leading to significant changes in processor interfaces.
Let us consider the relevant example of hardware extensions for messaging. Message-passing software communications naturally correspond to data queues, but can also be implemented through a global shared memory, where messages are written and read by accessing the bus. In this case, the synchronization overhead is also significant, and translates into more bus traffic as well. Direct processor-to-processor connections reduce communication cost and latency by allowing data to move directly from one processor's registers to the registers and execution units of another.
The highest-bandwidth mechanism for task-to-task communication is hardware...
