Network-on-chips (NoC) architectures are emerging as a strong candidate for the highly scalable, reliable, and modular on-chip communication infrastructure platform to implement high-performance SoCs. There have been many architectural and theoretical studies on NoCs such as design methodology, topology exploration, quality-of-service (QoS) guarantee and low-power design. All of those are discussed in the previous chapters in this book. In this last chapter, we would like to introduce the silicon chip implementation trials for NoC-based Systems-on-chip (SoCs). We will discuss both academic and industrial design efforts, even though academic design are dominant. This is because NoC technology is still maturing and for the time being commercial SoC products have relied on mature and well-established bus-based interconnects. However, we have seen in the previous chapter that several industrial efforts are under way to develop the standardized protocol specifications, EDA tool chains and Internet Protocol (IP) library supports for next-generation NoC-based products.

9.1 Kaist Bone Series

For the unique purpose of realizing the new NoC technology through implementation, the BONE (Basic On-chip Network) project was launched in 2002 at KAIST (Korea Advanced Institute of Science and Technology, Daejeon, Korea). As the results of the project, new NoC techniques and the implementations have been published and demonstrated in every year as summarized in Fig. 9.1.

Figure 9.1: BONE series road map since 2002.

This project covers circuit-level design, architectural researches and system integration on an NoC platform. In this section, each generation will be overviewed and for the more detail...