Overview

Recent drive for "smaller, faster, cooler and cheaper" semiconductor technology achieves commercialization of 65 nm process and soon 45 nm process will be adopted in mass production by the industry [23] such deep submicron (DSM) technology brings up many new challenges and an increase of uncertainty (i.e., unpredictability) in process, design and market. The precise control of the fabrication process is almost impossible so that fluctuation of the dopant concentration, variation of the photolithographic resolution and thin film thicknesses are indispensable and become the causes of uncertainties in threshold, g _m and I _DSAT of MOSFET. The same problems can take place to interconnection lines implemented with 6 7 layers of metals, or polysilicon and diffusion layers. The process uncertainty leads to non-uniformity of the sheet resistance and increase of the coupling noises among interconnects. In addition, decreasing interconnect pitch and increasing aspect ratio with the technology advance accelerates these issues further. The interconnect is used to distribute clock and signals, and to provide power and ground to and among many functional blocks on a chip. Copper wires and low k material are widely used for the control of RC delays but still cannot meet the high-speed transmission needs with scaling of feature sizes. How to isolate those process dependent problems in interconnect from the performance of the system on chips (SoC) is the critical points in SoC design.

According to an ITRS prediction illustrated in Fig. 3.1, the gap between interconnection delay and the...