TABLE OF CONTENTS This section focuses on the point-to-point communication protocol between an NI and the connected processor cores. This kind of protocol specifications is quite recent, and represents the latest evolution stage of industry-wide communication protocols for multiprocessor SoCs. Interestingly, this stage has introduced a paradigm shift in protocol specifications that can potentially speed up the development and industrial adoption of NoCs.
Let us follow the evolution of system interconnect protocols by observing the features introduced by successive releases of AMBA protocol specifications [43]. The family of AMBA protocols represents the de facto standard for the design of communication architectures for highperformance embedded microcontrollers.
AMBA AHB is one of the first protocol specifications released by ARM, and supports the efficient connection of processors, on-chip memories, and off-chip external memory interfaces with low-power peripheral macrocell functions. AMBA AHB assumes that the system backbone consists of a shared communication resource connecting multiple system cores. The structure of an AHB-compliant bus is reported in Fig. 6.2(a).
This bus specification defines two split and unidirectional data links (one for reads and one for writes), but only one of them can be active at any time. Only one bus master can own the data wires at any time, preventing the multiplexing of requests and responses on the interconnect signals. Transaction pipelining (i.e., split ownership of data and address lines) is supported to provide for higher throughput. In practice, each transaction consists of...
