TABLE OF CONTENTS Two primary methods are used for FPGA design validation: simulation and board-level testing. Board-level testing is implemented after the design has been placed and routed and is performed on the target hardware platform. Although board-level testing is an effective design test and debug approach, validating a design in the lab at the board level all at once without significant block-level testing is only practical for small to medium designs with limited complexity. Simulation plays a critical role in the FPGA design verification process, especially for rapid system development efforts. We will focus on design simulation in this chapter. Board-level validation will be discussed in more detail in Chapter 11.
The primary benefit simulation provides is the ability to begin validation of design functionality at the earliest phases of the project, independent of the availability of a hardware target platform. Simulation can begin before the synthesis process and can continue throughout all the implementation phases of the FPGA design flow until a hardware target platform becomes available.
There are three main stages of simulation. Each of these stages is related to the phases of implementation relative to the synthesis process. The typical terms associated with each simulation stage are behavioral, functional and timing. Traditionally, behavioral simulation occurs before the synthesis process, while functional simulation occurs immediately following synthesis. Timing simulation occurs after the place-and-route design stage. Behavioral and functional simulations perform the functions they describe by validating high-level behavior and lower-level functionality, respectively. Timing simulation,...
