13.1 Overview

FPGA intellectual property (IP) can be defined as a reusable design block (hard, firm or soft) with a fixed-range of functionality. The term IP usually refers to a pre-verified functional design block that is obtained from a group outside the local design team. An exception to this can occur when a design block is being incorporated from a different in-house project. Also, IP usually implies some level of previous testing, although this is not an absolute requirement. Available IP offerings cover a wide range of design applications and functionality. Common terms used to describe IP blocks include library parameterized modules (LPMs), megafunctions, macros, relationally placed macros (RPMs), cores, and synthesizable cores. Two primary potential benefits of IP use are reduced design schedule and design, and development cost and risk.

IP can be leveraged to shorten project schedules by eliminating design block development and testing time. The potential project benefit, for each IP application is influenced by several factors, including how well the implemented functionality and performance of the IP block matches project requirements, the level of IP testing, the number of times an IP block has been implemented, and the IP cost, licensing and documentation.

This chapter discusses some of the trade-offs, decisions and design team actions that must be completed by the design team to implement design functionality with IP blocks. Table 13.1 presents a high-level design task flow for qualifying, selecting, implementing and testing IP.