Appendix A: Rapid System Prototyping Technical References

Prefix Index

Search On: Topics to search on within the Manufacturer web page

XAPP: Xilinx Application Note

AN: Application Note

CP: Conference Paper

WP: White Paper

TechXclusives: Xilinx Special Topic

TN: Tech Note

AB: Application Brief

QN: Quick Notes

TB: Tech Brief

AN: Board Level Considerations for Actel FPGAs	Board	Actel	CH 6
AN: Simultaneous Switching Noise and Signal Integrity	Board	Actel	CH 6
AN 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices	Board	Altera	CH 6
AN 384: Using Calibrated Series On-Chip Termination in Stratix -II Devices	Board	Altera	CH 6
AN 315: Guidelines for Designing High-Speed FPGA PCBs	Board	Altera	CH 6
AN 224: High-Speed Board Layout Guidelines	Board	Altera	CH 6
AN 114: Designing with High-Density BGA Packages for Altera Devices	Board	Altera	CH 6
AN 90: SameFrame Pin-Out Design for FineLine BGA Packages	Board	Altera	CH 6
AN 81: Reflow Soldering Guidelines for Surface-Mount Devices	Board	Altera	CH 6
AN 75: High-Speed Board Designs	Board	Altera	CH 6
WP: Input Signal Edge Rate Guidance	Board	Altera	CH 6
WP: Basic Principles of Signal Integrity	Board	Altera	CH 6
WP: Board Design Guidelines for LVDS Systems	Board	Altera	CH 6
AN 358: Thermal Management for 90-nm FPGAs	Board	Altera	CH 6
AN 353: Reflow Soldering Guidelines for Lead-Free Packages	Board	Altera	CH 6
AN 185: Thermal Management Using Heat Sinks	Board	Altera	CH 6
AN6012: Analog Layout and Grounding Techniques	Board	Lattice	CH 6
AN6019: Differential Signaling	Board	Lattice	CH 6
AN: Ground Bounce	Board	Lattice	CH...

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