TABLE OF CONTENTS As FPGA designs increase in size and complexity, the board-level testing effort also increases in complexity. As previously discussed, the design verification phases of a typical FPGA design project including simulation, debug and verification can comprise 40% or more of the overall design cycle. By increasing the efficiency of the verification design phases, the design cycle can be dramatically reduced.
A well-planned design will require some minimum number of hours to verify. The closer a design verification phase can be held to this standard, the shorter the schedule. However, for a poorly conceived or implemented design there is essentially no upper limit in terms of time and resources that may be required to verify a design; this can cause a design schedule to expand exponentially. Poorly implemented designs will be difficult to simulate, integrate and debug.
To reduce this potentially unbounded schedule and cost risk, it is important to include every design element that can assist in the design integration, debug and verification phases. The increased complexities of advanced FPGA families result in more complex design integration and debug challenges. Complex digital circuits require efficient debugging. The planning and preparation for the design, debug and verification efforts should start at the earliest phases of the design cycle. A design verification plan should be developed in parallel with the design requirements definition. The design verification plan should present plans for design simulation, integration, debug and verification including expected results.
The board-level hardware design should include both hardware and software...
