Digital Integrated Circuit Design from VLSI Architectures to CMOS Fabrication

A computation that depends on the present arguments exclusively is termed combinational. A sufficient condition for combinational behavior is a DDG which is free of circular paths and where all edge weights equal zero.
Consider some fixed but otherwise arbitrary combinational function y( k) = f( x( k)). The DDG in fig. 2.12a depicts such a situation. As suggested by the dashed edges, both input x( k) and output y( k) can include several subvectors. No assumptions are made about the complexity of f which could range from a two-bit addition, over an algebraic division, to the Fast Fourier Transform (FFT) operation of a data block, and beyond. In practice, designers would primarily be concerned with those operations that determine chip size, performance, power dissipation, etc. in some critical way.
The isomorphic architecture simply amounts to a hardware unit that does nothing but evaluate function f, a rather expensive proposal if f is complex such as in the FFT example. Three options for reorganizing and improving this unsophisticated arrangement exist. [24]
Decomposing function f into a sequence of subfunctions that get executed one after the other in order to reuse the same hardware as much as possible.
Pipelining of the functional unit for f