TABLE OF CONTENTS Physical design is concerned with turning circuit netlists into layout drawings that
Are amenable to fabrication with some given target process,
Logically function as expected in spite of numerous parasitic effects,
Meet ambitious performance goals in spite of layout parasitics, and
Keep fabrication costs down by minimizing die size and by maximizing yield.
The degree to which physical issues are placed under control of IC designers is highly dependent upon fabrication depth and design level. While global interconnect must be planned for in every design project even when opting for field-programmable logic few digital designers continue to work with layout at the detail level today. This chapter is organized accordingly. Sections 11.2 through 11.4 cover issues that are relevant in any IC design, such as floorplanning and packaging, while the material on detailed layout is postponed to section 11.5. Section 11.6, finally, collects discussions of various destructive phenomena that must be contained.
The layers made available by VLSI processes greatly differ in their geometric and electrical characteristics. Let us begin by studying those properties and differences.
The transfer of layout patterns to the various layers of material on a semiconductor die is obtained from photolithographic methods followed by selective removal of unwanted material. Numerous effects concur to limit the achievable resolution:
Tolerances and misalignments of photomasks,
Wave diffraction and proximity effects,
Uneven profile together with shallow depth...
