TABLE OF CONTENTS Unlike combinational computations, the outcome of sequential computations depends not only on present but also on past values of its arguments. Architectures for sequential computations must therefore include memory. In the DDG this gets reflected by the presence of edges with weights greater than zero. However, as nonrecursiveness implies the absence of feedback, the DDG remains free of circular paths. The storage capacity required by the isomorphic architecture is referred to as memory bound because no other configuration exists that could do with less. [52] Table 2.9 allows approximate translation from memory bits to chip area.
The presence of registers in a circuit suggests a new type of reorganization known as retiming or as register balancing, whereby registers get relocated so as to allow for a higher computation rate without affecting functionality [52] [53]. The goal is to equalize computational delays between any two registers, thereby shortening the longest path that bounds the computation period from below. Referring to a DDG one must therefore know.
In what way is it possible to modify edge weights without altering the original functionality?
Let us follow an intuitive approach to find an answer. [53] Consider a DDG and pick a vertex, say h in fig. 2.24, for instance. Now suppose the operation of vertex h is made to lag behind those of all others by adding latency to every edge pointing towards that vertex, and by removing the same...
