Digital Integrated Circuit Design from VLSI Architectures to CMOS Fabrication

2.10: Problems

2.10 Problems

  1. Computationally efficient approximations for the magnitude function have been presented in table 2.8. (a) Show that approximation 2 remains within 3% of the correct result for any values of a and b. (b) Give three alternative architectures that implement the algorithm and compare them in terms of datapath resources, cycles per data item, longest path, and control overhead. Assume input data remain valid as long as you need them, but plan for a registered output. Begin by drawing the DDG.

  2. Discuss the idea of combining replication with pipelining. Using fig. 2.18 and the numbers that come along with it as a reference, take a pipelined datapath before duplicating it. Sketch the result in the AT-plane for various pipeline depths, e.g. for p = 2, 3, 4, 5, 6, 8, 10. Compare the results with those of competing architectures that achieve similar performance figures (a) by replicating the isomorphic configuration and (b) by extending the pipeline approach beyond the most efficient depth. How realistic are the various throughput figures when data distribution/recollection is to be implemented using the same technology and cell library as the datapath?

  3. Reconsider the third-order correlator of fig. 2.25a. (a) To boost performance, try to retime and pipeline the isomorphic architecture without prior reversal of the adder chain. How does the circuit so obtained compare with fig. 2.25d. Give estimates for datapath resources, cycles per data item, longest path, latency, and control overhead. (b) Next assume...

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