TABLE OF CONTENTS Up to this point, we have have ignored the difficulties of distributing a clock signal over a chip or a major portion thereof. We were in good company as systems engineering, automata theory, and other theoretical underpinnings of digital design assume simultaneous updating of state throughout a circuit. Physical reality is different from such abstractions, though.
Consider a population of flip-flops or other clocked subcircuits that make part of one clock domain in a synchronous design as shown in fig. 6.1. A common clock tells them when to transit into the next state. Ideally, all such bistables are supposed to react to the clock instantly and all at exactly the same moment of time.
In practice, however, switching will be retarded due to many small delays inflicted by drivers and wires in the clock distribution network. As most clock signals connect to a multitude of storage elements spread out over an entire clock domain, individual switching times will differ because delays along the various clock propagation paths are not quite the same. This scattering over time is loosely referred to as clock skew. To make things worse, those delays will slightly vary from one clock cycle to the next, thereby giving rise to clock jitter.
Many causes contribute to the timewise scattering of clocks:
Unevenly distributed fanouts and...
