TABLE OF CONTENTS Industry has seen increasing levels of integration at the chip level with SoC devices for wireless communications. As a result, the production testing methodologies of the RF portions of these SoC devices have been impacted, introducing new challenges while at the same time offering advantages in terms of the cost of testing (COT). Some of the areas that need to be considered are new philosophies surrounding system-level testing, wafer probing of known- good die, more consideration of final test needs (such as concurrent testing) by chip design engineers, design for testability and built-in self-test, and how this increased integration drives the architectures of test systems. These areas will be addressed, and considerations for production testing that can align seamlessly with and even take advantage of this increased integration will be presented along with the associated implications for COT.
The purpose of this chapter is to enlighten the reader to the impact that integration of electronic devices is having on production testing of these devices. In particular, major shifts in testing methodologies for RF devices are becoming available. A few key topics surrounding production testing are discussed in the following sections:
System-level testing;
RF wafer probing;
SiP versus SoC architectures;
Designers' new responsibilities;
RF built-in self-test;
Impact on test system architecture;
Testing wide bandwidth devices.
Modern highly integrated chips/packages have an "RF-to-bits" or RF-to-analog baseband architecture. One of the largest impacts of this RF integration is that it provides testers with the opportunity to take advantage of a...
