INSTRUCTION SET ARCHITECTURE

The Itanium processor s instruction set architecture (ISA) is designed with new features to enhance instruction level parallelism (ILP), increase software performance, and allow the compiler to communicate information to the processor. In earlier chapters, you saw that features such as predication, speculation, loop pipelining, and branch predication increase ILP. Other capabilities that provide special support for software modularity, such as register stack switching, high performance floating-point instructions, and specific multimedia instructions, enable higher performance. Finally, communication between compiler and processor is facilitated by template information contained in the instruction bundles. The template information allows the processor to efficiently assign its functional units to the execution of instructions. All these features are elements of the ISA.

The instructions of the assembly language instruction set are another element of the ISA. For orderly presentation, related instructions in the instruction set are arranged in groups, as follows:

• Memory access instructions

• Register file transfer instructions

• Integer computation instructions

• Character strings and population count instructions

• Compare instructions

• Branch instructions

• Multimedia instructions

The instruction set also includes floating-point instructions; however, they are covered in Chapter 9, which is dedicated to the floating-point programming model...