Itanium Architecture for Software Developers

The Itanium processor s floating-point hardware includes four independent floating-point execution units two extended-precision units and two single-precision units and a large, dedicated file of registers. These resources deliver world-class performance peak performance of 3 gigaflops for extended precision or 6 gigaflops for single precision. The Itanium processor s floating-point architecture is fully compliant with the ANSI/IEEE Standard for Binary Floating- point Arithmetic (Std. 754-1985). To further enhance the performance of floating-point applications, the Itanium architecture includes extensions such as a combined multiply and add instruction, minimum and maximum calculation instructions, and instructions that enable high-bandwidth memory accesses. This chapter examines the floating-point data types, the register resources, and the operations that are performed by the floating-point instructions.
Floating-point numbers are called real numbers because they can represent signed integers, fractions, or mixed numbers. Floating-point notation represents numbers written in scientific notation. A floating-point number contains three elements: a sign, biased exponent, and significand. The Itanium architecture supports a variety of numeric formats. These variations include IEEE compatible single-precision real numbers, double-precision real numbers in hardware, and quad precision through software. In addition to the IEEE real number data types, the architecture directly supports signed and unsigned 64-bit integers, and an 82-bit floating-point register format. Instructions can be combined to implement 128-bit floating-point arithmetic operations efficiently, but that is beyond the scope of this book.
These floating-point number types differ in the ranges and coding allowed for the biased exponent and the number of bits of...