Itanium Architecture for Software Developers
This unique description of the Intel Itanium application architecture helps the software development community to use the power of Intel s new line of 64-bit processors.
TABLE OF CONTENTS Itanium Architecture for Software Developers
FLOATING-POINT REGISTER FORMAT AND DATA TYPES ENCODING
In the last section, we introduced the registers that are involved in floating-point operation, and noted that the source and destination operands of floating-point computations are held in the registers of the floating-point register file. This data can be either integer or real-type numbers. This section continues the study of the Itanium processor s floating-point architecture by examining the organization of data held in the floating-point registers.
Floating-point Register Format
Earlier, we pointed out that the Itanium architecture supports an 82-bit floating-point register format. This format is designed to accommodate both integer and real-type numbers. Remember that the three elements of a real-type floating-point number are the sign bit, biased exponent, and significand. Figure 9.5 shows how the floating-point registers are partitioned to accommodate these fields. Notice that the 64 least significant bits, b 0 through b 63, hold the significand. The next 17 bits,b 64 through b 80 contain the biased exponent, and the most-significant bit, b 81, is the sign bit. The significand field is composed of an explicit integer bit (b 63) and 63 bits for the fraction part of the significand(b 0 through b 62).
Figure 9.5: Format of a Floating-point Register
This floating-point register format has enough bits to represent a variety of different types of floating-point values. Table 9.11 shows the types of values, whether or not they are supported, and how they are encoded. The different value types...
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