Itanium Architecture for Software Developers
This unique description of the Intel Itanium application architecture helps the software development community to use the power of Intel s new line of 64-bit processors.
TABLE OF CONTENTS Itanium Architecture for Software Developers
Chapter 5: Memory Access and Register Transfer Instructions
The Itanium architecture requires all memory-to-register information transfers to take place between a storage location in memory and a register in the general register or floating-point register files. For this reason, a general register or floating-point register must act as an intermediary for transfers of data between memory and any other internal registers, such as the predicate registers, branch registers, or application registers. This chapter explains the instructions that facilitate transfer of information between memory and registers. These instructions are grouped as the memory access instructions and register transfer instructions.
MEMORY ACCESS INSTRUCTIONS
Memory access instructions can only process information in the general and floating-point register files. The instructions that are used to load data from memory, save data in memory, or modify information directly in memory are called the memory access instructions. This group includes the load, store, and semaphore instructions. The first part of this chapter examines the operation of the instructions in each of these subgroups with respect to the general registers. Their use with the floating-point registers will be covered in a later chapter.
LOAD INSTRUCTION
The load instruction transfers data from a source operand in memory to a destination operand that is a general register. The base mnemonic for the instruction, which is ldsz, and its general formats are shown in Table 5.1.
| Mnemonic | Operation | Format |
|---|---|---|
| ldsz | Load | (qp) ldsz.ldtype.ldhint r1=[r3] |
| (qp) ldsz.ldtype.ldhint r1=[r3],r2 | ||
| (qp) ldsz.ldtype.ldhint r1=[r3],imm9 | ||
| (qp) ld8.fill.ldhint r1=[r3] | ||
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