In Chapter 8, we examined the operation of the parallel data arrangement instructions. The instruction set provides other instructions that rearrange data, but they process floating-point data in the floating-point registers. Table 9.22 lists the six floating-point data arrangement instructions and their instruction formats. Note that each instruction performs its respective data arrangement operation merge, mix, pack, swap, or sign extend on the significands of the floating-point numbers in source registers specified by f2 and f3 and places the result in the significand of the destination register identified by f1. If either source operand of the data arrangement instruction equals NaTVal, the result produced in the destination operand is NaTVal, not the computed result.