Itanium Architecture for Software Developers
This unique description of the Intel Itanium application architecture helps the software development community to use the power of Intel s new line of 64-bit processors.
TABLE OF CONTENTS Itanium Architecture for Software Developers
Chapter 7: Compare and Branch Instructions
Chapter 6 introduced the integer computation instructions of the Itanium processor s instruction set. In this chapter, we continue our study of the ISA with the compare and branch instruction groups. A number of software structures and architectural capabilities are also introduced in conjunction with these instructions. They include: predication; elimination of branches with predication; register stack and the function call process; counted, while, and pipelined loops; and rotating registers.
QUALIFYING INSTRUCTION EXECUTION WITH A PREDICATE
In Chapter 1, we introduced predication as the method by which the execution of an instruction is made conditional. The chapters that followed showed that predicates are one-bit values and are stored in the predicate register file. Also, the execution of most instructions could be gated by a qualifying predicate. A 0 predicate is interpreted as False and a 1 predicate is interpreted as True. If the predicate is True, the instruction executes normally. If the predicate is False, the instruction does not modify the application state.
We have found that the predicate register used to determine whether or not an instruction is executed is specified in the instruction format by an optional qualifying predicate. Some examples of predicated
instructions are:
(p1) add r1=r2,r3(p2) ld8 r5=[r7](p3) chk.s r4,recovery
For instance, if the state of Pr 1 is True when the first instruction is executed, the add operation is performed normally and the state of register Gr 1 is updated with the result produced by adding the values in Gr
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