Itanium Architecture for Software Developers
This unique description of the Intel Itanium application architecture helps the software development community to use the power of Intel s new line of 64-bit processors.
TABLE OF CONTENTS Itanium Architecture for Software Developers
FLOATING-POINT APPLICATION PROGRAMMING MODEL
Chapter 3 introduced the application registers of the Itanium processor. At that time, we did not cover the registers that are provided to support the floating-point architecture. The registers that are used during floating-point operations are those in the floating-point register file, the floating-point status register, and control bits in the user mask. This section describes each of these register resources, their function, and instructions that affect their operation.
Floating-point Register File
The registers in the floating-point register file are used to hold source and destination operands for floating-point computations. Figure 9.1 shows the structure of the floating-point register file. Notice that it contains 128 independent floating-point registers, which are labeled Fr 0 through Fr 127. Each of these registers is 82 bits wide. The large floating-point register file reduces the number of load and store operations in applications and results in increased floating-point performance. Programs at all privilege levels can access data in the floating-point registers.
Figure 9.1: Floating-point Register File
Similar to the general register file, the floating-point register file is organized into two partitions. In this case, they are called the static registers and rotating registers. Registers Fr 0 through Fr 31 are used for the static part of the floating-point register file. Fr 0 and Fr 1 have fixed values, and when accessed as a source operand, their values are always read as +0.0 and +1.0, respectively. If either of these registers is used...
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