TABLE OF CONTENTS Conventional bulk CMOS technology is still (and will be for the next few years) prevalent in the microelectronics industry. According to the International Technology Roadmap for Semiconductors (ITRS 2004 update [1]), bulk MOS transistors will still be used for the 45 nm technology node (gate length around 18 nm), which is expected to be running by 2010. The feasibility of 15 nm conventional MOS transistors in bulk CMOS technology has already been demonstrated [2]. Thus, dopant fluctuation in the depletion region will be the dominant factor for the random variations of next generations bulk CMOS processes. By focusing mainly on the prevailing cause of parameter fluctuations, we intend to provide circuit designers with a mismatch model that is very simple and easy to use for hand-calculations.
Mismatch is the denomination of time-independent variations between identically designed components. The performance of most analog or even digital circuits relies on the concept of matched behavior between identically designed devices [3], [4], [5], [6]. In analog circuits, the spread in the dc characteristics of supposedly matched transistors results in inaccurate or even anomalous circuit behavior [4]. Also, for digital circuits, transistor mismatch leads to propagation delays whose spread can be of the order of several gate delays for deep-submicron technologies [4], [7]. The shrinkage of the MOSFET dimensions and the reduction in the supply voltage make matching limitations even more important. As predicted by Professor J. Meindl [8], variations will set the ultimate limits on scaling of MOSFETs.
Manufacturing variations...
