TABLE OF CONTENTS In the previous chapters we developed the models for the conventional bulk CMOS transistor. This chapter presents, in some detail, different MOSFET structures and their modeling issues. Firstly, we summarize some (deep) submicron planar MOS structures. We then review the silicon-on-insulator (SOI) MOSFET. Finally, we introduce some innovative MOS devices that may replace the conventional MOS transistor in deeply scaled CMOS technologies. It is shown that the charge based model, with some minor variations, is appropriate for all the different MOS structures herein.
Physics places constraints on the conventional bulk MOS transistor for deeply scaled technologies. To keep pace with the MOSFET scaling predicted by the International Technology Roadmap for Semiconductors [1], new materials and devices have been and will have to be introduced. Shrinking MOS transistors beyond the 50 nm technology node poses some challenges for the semiconductor industry such as (i) quantum-mechanical tunneling of carriers through the thin gate oxide, from source to drain, and from drain to the body of the MOSFET; (ii) control of the dopant number fluctuations; (iii) increased short-channel effects such as DIBL, and (iv) a reduction in the on-off current ratio [2], [3]. To overcome these challenges, modifications to the classical bulk MOS transistor have been proposed. We will focus the next sections on modeling such non-classical CMOS devices as fully depleted SOI transistors, surrounding-gate transistors, and multiple-gate FETs. Before presenting these non-classical CMOS devices, we will discuss some technological modifications to the conventional bulk CMOS transistor that have allowed...
