For oxides below 4nm, high current leakages through the oxide can occur due to the quantum mechanical tunneling of electrons. The gate leakage current can not only negatively affect the device performance [28] but can also significantly increase the standby power consumption of a chip. For these reasons a compact model for the gate current is mandatory for advanced technologies. Although the compact modeling of the gate tunneling currents is a relatively new subject, the characterization and modeling of gate tunneling currents is not. Beginning with the pioneering work of Lenzlinger and Snow [1], numerous researchers have analyzed electron tunneling current in MOS structures, but most of the literature has focused on thick oxides and high applied voltages. The tunneling models for thick oxides are not adequate for thin oxides because of the differences in the potential barrier shapes and transport mechanisms.

In this chapter we will first briefly review tunneling through a potential barrier. A compact model for tunneling in MOS structures is then developed and a brief comparison of the main tunneling models is carried out. The last topic of the gate current section is the analysis of the different components of the gate current. The other subject of the chapter is the bulk current. The two main mechanisms at the origin of bulk current, namely gate-induced drain leakage (GIDL), and impact ionization current, are presented.