TABLE OF CONTENTS Unfortunately, the previous derivation is a little too simplistic to model the actual emitter follower when loaded with a capacitance. In particular, we have neglected two important transistor parameters that have a serious effect on this circuit. The first is the collector-base (or drain source) capacitance, C j, and the second is the bulk resistance in the emitter (source), R eb. Our simple models are based on a transistor f t measurement where both the emitter and collector are at AC ground. For this circuit, the emitter in particular is not at AC ground, and so C j cannot be neglected. We will add back this parameter by making use of Miller's theorem, which lets us model the effect of C j by adding a capacitor of value C j (voltage gain for base to collector in this circuit is 0) from the base node to ground. A modification of the network in Figure 2-16 is shown in Figure 2-17 to take into account the addition of C j. Since C j can be added to either side of R b, I have chosen the node closest to the junctions in part because it offers a "worst case" challenge, and also because it is easier to work with afterward. In any case, the consequence of placement is likely to be quite small.
