TABLE OF CONTENTS The techniques discussed in the preceding section, which employed multiplexers as the means of improving the controllability and/or observability of internal nodes of a circuit when under test, have the severe disadvantage of requiring many more I/Os to be provided on the circuit to give this improved testability. Scan-path testing, sometimes referred to as scan test is a means of overcoming this disadvantage and reducing the additional I/Os required to a minimum irrespective of the size of the circuit being tested. As will be seen, the penalty will be an increase in the time to test the circuit, plus additional housekeeping in order to keep track of the serial input and output logic signals now involved.
Scan-path testing fundamentally covers sequential logic networks. Recall from Figure 3.14 that all such networks can be modelled by a combinational logic network and a storage (memory) network, with secondary inputs and outputs linking the two halves. The primary outputs may be a function of the storage circuit states only (a Moore model) or a function of both the storage circuit states and the primary inputs (a Mealy model), but this distinction will not concern us here.
Scan-path testing of such a network involves switching all the storage elements of the circuit from their normal mode to a test mode shift register configuration, A scan-in I/O and a scan-out I/O allow data to be read into and read out from this reconfiguration for test purposes, thus providing controllability and observability of...
