TABLE OF CONTENTS As has been seen in previous chapters, the principal difficulties with digital network testing are (i) the volume of the simulation data, and (ii) the volume of data which has to be checked at network outputs when under test. In this Chapter we will consider means which have been proposed to ease the task of checking the output response when under test, so that the very large number of individual 0 or 1 output bits do not have to be compared step by step against the expected (fault-free) response, such as is present in the test arrangements shown in Figures 3.2b and c. Again we shall largely be considering combinational circuits rather than sequential, the latter still requiring their own special testing consideration as will be discussed in Chapter 5. Some of the concepts that we will review in this Chapter have yet to be reflected in common practice, but all are part of the whole research and development effort which has taken place and still continues on testing strategies.
An ideal test procedure would be as shown in Figure 4.1a when one additional input pin is added to the network under test so as to switch it from normal mode to test mode, with one additional output pin to show the final result of the test, this being a simple pass or fail (fault-free or faulty) indication. Also, the ideal situation would require no failure of the pass/fail check circuit, all this being done with minimum...
