TABLE OF CONTENTS Referring back to Figure 4.10, it will be appreciated that we have now covered the extreme right-hand branch of this range of self-test strategies; in Chapter 4 we were concerned with online methods, which were particularly appropriate for critical systems that could not afford to have a faulty output or where a fault had to be immediately flagged, whereas in this present chapter offline techniques with a normal mode of system operation and a separate test mode of operation have been our principal interest. In general, fault detection but not fault location (except to within a separate circuit or subsystem) has been involved.
Design for testability (DFT) procedures have been seen to become necessary as circuit complexity has increased to the VLSI level. Automatic test pattern generation (ATPG) programs have been found to be increasingly unable to formulate an acceptable set of test vectors within a given CPU time for large circuits, and testers to apply test to complex circuits and monitor the results are themselves of increasing complexity and cost.
Partitioning of a large circuit into smaller parts which may be separately tested is therefore a natural solution to reduce the testing problem. However, as we have seen, the precise partitioning may be largely dictated by the actual circuit being designed, but separation of the combinational logic and the sequential (memory) elements is a basic consideration in most DFT strategies. Four aims and objectives are therefore present, namely:
to attempt to use the on-chip sequential elements...
