TABLE OF CONTENTS As has been seen, scan-path test methodologies do not eliminate the need to prepare some set of acceptable test vectors for the circuit under test, or the need for appropriate external hardware to apply the test stimuli and monitor the resulting response. They do, however, ease the problem of automatic test pattern generation by making the resulting test mode as nonsequential as possible, but at the expense of assembling the serial test data and the time required to execute the resulting tests. Boundary scan itself is not a direct testing procedure, but merely a recognised means of serially accessing internal modes and interconnections on a PCB or other system assembly.
Turning therefore to offline self test methodologies, the concept here is to build in appropriate means whereby the circuit under test can be switched from a normal mode of operation to a test mode, with the required test stimuli and the resulting response both being done on-chip without the need to generate any ATPG data based upon stuck-at fault modelling or other means, or apply it in series or parallel using some external hardware resource. The circuit under test becomes its own test vector generator and test response detector. A further advantage of this concept is that on-chip tests can be done using the normal system clock(s) and at the full speed of the normal system.
This built-in self test (BIST) methodology becomes increasingly significant or necessary as VLSI chip size and complexity increases. We...
