5.8 References

1. BENNETTS, R.G.: 'Design of testable logic circuits' (Addison-Wesley, 1984)

2. GIACOMO, J.D.: 'Designing with high performance ASICs' (Prentice Hall, 1992)

3. NEEDHAM, W.M.: 'Designer's guide to testable ASIC devices' (Van Nostrand Reinhold, 1996)

4. Parker, K.P.: 'Integrating design and test: using CAE tools for ATE programming' (IEEE Computer Society Press, 1987)

5. 'Design for testability'. Microelectronics for industry publication PT.505DFT, The Open University, UK, 1988

6. ABRAMOVICI, M., BREUER, M.A., and FRIEDMAN, A.D.: 'Digital systems testing and testable design' (Computer Science Press, 1990)

7. 'Design for testability' in 'Design handbook' (Intel Corporation, 1986)

8. Testing and testability' (NEC Electronics Corporation, 1986)

9. 'Data book and design manual' (LSI Logic Corporation, 1986)

10. BERGLUND, N.C.: 'Level sensitive scan design test chip/board systems', Electronics, 1979, 52, 15 March, pp. 118-120

11. FUNATSU, S., WAKATSUKI, N., and YAMADA, A.: 'Easily testable design of large digital circuits', NEC Res. Dev., 1979, (54), pp. 49-55

12. FUJIWARA, H.: 'Logic testing and design for testability' (MIT Press, 1985)

13. MICZO, A.: 'Digital logic testing and simulation' (Harper and Row, 1986)

14. PYNN, C.: 'Strategies for electronic test' (McGraw-Hill, 1986)

15. WILLIAMS, T.W. (Ed.): 'VLSI testing' (North-Holland, 1986)

16. WILLIAMS, T.W., and PARKER, K.P.: 'Design for testability-a survey', Proc. IEEE, 1983, 71, pp. 98-112

17. EICHELBERGER, E.B.: 'Latch design using level sensitive scan design'. Proceedings of COMCON, 1983, pp. 380-383

18. DASGUPTA, S., GOEL, p., WALTHER, R.G., and WILLIAMS, T.W.: 'A variation of LSSD and its implications on design and test pattern generation in VLSI'. Proceedings of IEEE international conference on Test, 1982, pp.