VLSI Testing: Digital and Mixed Analogue/Digital Techniques

Partitioning of a circuit or system and other ad hoc design methods consist largely of a number of recommended or desirable practices which a designer should consider at the design phase. There are, therefore, no underpinning mathematical developments or equations to support these practices, but much more a list of recommended do and don'ts which the experienced designer follows. The general objective is simple, being to provide increased controllability and observability of the circuit or system being designed.
One of the most obvious and intuitive techniques for easing the testing problem is to partition the overall circuit or system into functional blocks, each of which may be independently tested. It is generally accepted that test costs are proportional to the square of the number of logic gates in a circuit and hence partitioning a circuit into, say, four equal parts reduces the testing problems of each part by a factor of sixteen compared with the overall circuit. How this may be done and how many partitions are practical obviously depends upon the specific circuit being designed.
The penalty for the partitioning and separate test of partitions is that additional I/O pins may be required to give access to the partition boundaries. This in turn may require the incorporation of multiplexers within the circuit to switch lines from their normal mode to a test mode, for example as shown in Figure 5.1. This may be particularly necessary in the design of complex standard...