5.1 General introduction

Because of the difficulties or complexities encountered when formulating acceptable tests for integrated circuits as they become larger and more complex, it is now essential to consider testing at the design stage of a VLSI circuit or system using VLSI parts, and not as an afterthought once the design has been completed. The old-fashioned separation between a design engineer who designs a circuit or system and a test engineer in a separate office who takes the design and then attempts to formulate an acceptable test strategy for it is no longer viable.

Design for testability, sometimes called design for test and almost always abbreviated to DFT, is therefore the philosophy of considering at the design stage how the circuit or system shall be tested, rather than leaving it as a tack-on exercise at the end of the design phase.

DFT techniques normally fall into three general categories, namely:

1. ad hoc design methods;

2. structured design methods;

3. self test.

The first two of these methods usually require the use of some external comprehensive test facility, such as the tester illustrated in Figure 1.4 for VLSI circuits, but the third method usually minimises to a considerable extent the use of external test resources.

We will look at these three DFT categories in the following sections.