Digital Circuit Design with an Introduction to CPLDs and FPGAs

The JK flip flop is perhaps the most popular type. Basically, the JK flip flop is a modification of the clocked (synchronous) SR flip flop where one of the two inputs designated as J behaves like an S (set command), and the other input K behaves like an R (reset command). Its most important characteristic is that any combination of the inputs J and K produces a valid output. We recall that in a NAND-gated SR flip flop the input combination S=R=0 must be avoided, whereas in a NOR-gated SR flip flop the input combination S=R=1 must be avoided. In a JK flip flop however, it is perfectly valid to have J=K=0 simultaneously, or J=K=1 simultaneously.
Figure 8.7 shows is a basic JK flip flop constructed from a basic NOR-gated SR flip flop and its characteristic table is shown in Table 8.4.
| Inputs | Present State | Next State | ||
|---|---|---|---|---|
| J | K | Q n | Q n+1 | |
| 0 | 0 | 0 | 0 | No Change |
| 0 | 0 | 1 | 1 | No Change |
| 0 | 1 | 0 | 0 | No Change |
| 0 | 1 | 1 | 0 | Reset (or Clear) |
| 1 | 0 | 0 | 1 | Set |
| 1 | 0 | 1 | 1 | No Change |
| 1 | 1 | 0 | 0 | Toggle (State change) |
| 1 | 1 | 1 | 1 | Toggle (State change) |
The characteristic table of Table 8.4 reveals that the JK flip flop behaves as the SR flip...