Digital Circuit Design with an Introduction to CPLDs and FPGAs

8.8: Master/Slave Flip Flops

8.8 Master/Slave Flip Flops

A master/slave flip flop consists of two basic clocked flip flops. One flip flop is called the master and the other flip flop the slave. Figure 8.12 is a block diagram of a master/slave flip flop where the subscript M stands for master and subscript S for slave.

Figure 8.12: Master/Slave flip flop

The master/slave circuit operates as follows:

Whenever the Clock Pulse CP is logic 0 the master flip flop is disabled but the slave flip flop is enabled since CP is logic 1. Therefore, Q S=Q M, and also Q S= Q M, that is, the slave flip flop assumes the state of the master flip flop whenever the clock pulse is Low. When the clock pulse is logic High, the master flip flop is enabled and the slave flip flop is disabled. Therefore, as long as the clock pulse is High, the clock pulse input to the slave is disabled and thus the master/slave output Q S will not change state. Finally, when the clock pulse returns to 0 the master is again disabled, the slave is enabled and assumes the state of the master.

The SN74LS70 IC device is a JK flip flop which is triggered at the positive edge of the clock pulse. Its logic diagram is shown in Figure 8.13 and its symbol is shown in Figure 8.14.

Figure 8.13: Logic diagram for the SN7470 JK flip flop (Courtesy Texas Instruments)