Digital Circuit Design with an Introduction to CPLDs and FPGAs

8.7: Edge-Triggered Flip Flops

8.7 Edge-Triggered Flip Flops

Edge triggering uses only the positive or negative edge of the clock pulse. Triggering occurs during the appropriate clock transition. Edge triggered flip flops are employed in applications where incoming data may be random. The SN74LS74 IC device shown in Figure 8.10 is a positive edge triggered D type flip flop and the timing diagram of Figure 8.11 shows that the output Q goes from Low to High or from High to Low at the positive edge of the clock pulse.


Figure 8.10: The SN74LS74 positive edge triggered D-type flip flop with Preset and Clear (Courtesy Texas Instruments)

Figure 8.11: Timing diagram for positive edge triggered D flip flop

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