TABLE OF CONTENTS As mentioned earlier, a sequential circuit contains one or more flip flops and may or may not include logic gates. The circuits in Figure 8.20 are both sequential circuits.
The circuits of Figures 8.20(a) and 8.20(b) are both clocked by the clock pulse CP. The circuit of Figure 8.20(a) is also synchronous since the clock pulse CP is applied simultaneously at all three JK flip flops.
The analysis of synchronous sequential logic circuits is facilitated by the use of state tables which consist of three vertical sections labeled present state, flip flop inputs, and next state. The present state represents the state of each flip flop before the occurrence of a clock pulse. The flip flop inputs section lists the logic levels (zeros or ones) at the flip flop inputs which are determined from the given sequential circuit. The next state section lists the states of the flip flop outputs after the clock pulse occurrence. The procedure is illustrated with the following examples.
Describe the operation of the sequential circuit of Figure 8.21.
Solution:
First, we observe that the JK flip flops are enabled at the negative edge of the clock pulse. Also, the Set Direct S D and Reset Direct R D signals are asynchronous active Low inputs, that is, when they are Low, they override the clock and the data inputs forcing the outputs Q to a...
