Chapter 11: Introduction to Field Programmable Devices
This chapter is an introduction to Field Programmable Devices (FPDs) also referred to as Programmable Logic Devices (PLDs). It begins with the description and applications of Programmable Logic Arrays (PLAs), continues with the description of Simple PLDs (SPLDs) and Complex PLDs (CPLDs), and concludes with the description of Field Programmable Gate Arrays (FPGAs).
11.1 Programmable Logic Arrays (PLAs)
A Programmable Logic Array (PLA) is a small Field Programmable Device (FPD) that contains two levels of logic, AND and OR, commonly referred to as AND-plane and OR-plane respectively. In concept, a PLA is similar to a ROM but does not provide full decoding of the variables, in other words, a PLA does not generate all the minterms as a ROM does. [*] Of course, a ROM can be designed as a combinational circuit with any unused words as don't care conditions, but the unused words would result in a poor design. Consider, for example, the conversion of a 16-bit code into an 8-bit code. In this case, we would have 2 16=65536 input combinations and only 2 8=256 output combinations, and since we would only need 256 valid entries for the 16-bit code, we would have 65536-256=65280 words wasted. With a PLA we can avoid this waste.
The size of a PLA is defined by the number of inputs, the number of product terms in the AND-plane, and the number of the sum terms in the OR-plane. Figure 11.1 shows the block diagram of a...