Digital Circuit Design with an Introduction to CPLDs and FPGAs

Appendix D: Introduction to Boundary Scan Architecture

Overview

This appendix provides a brief overview of the boundary-scan architecture and the new technology trends that make using boundary-scan essential for the reduction in development and production costs. It also describes the various uses of boundary-scan and its application.

D.1 The IEEE Standard 1149.1

Boundary-scan, as defined by the IEEE Std. 1149.1 standard, is an integrated method for testing interconnects on printed circuit boards that is implemented at the IC level The inability to test highly complex and dense printed circuit boards using traditional in-circuit testers and bed of nail fixtures was already evident in the mid eighties. Due to physical space constraints and loss of physical access to fine pitch components and EGA devices, fixtures cost increased dramatically while fixture reliability decreased at the same time.

D.2 Introduction

In the 1980s, the Joint Test Action Group (JTAG) developed a specification for boundary-scan testing that was standardized in 1990 as the IEEE Std. 1149.1 1990. In 1993 a new revision to the IEEE Std. 1149.1 standard was introduced (titled 1149.1a) and it contained many clarifications, corrections, and enhancements. In 1994, a supplement that contains a description of the Bound-ary-Scan Description Language (BSDL) was added to the standard. Since that time, this standard has been adopted by major electronics companies all over the world. Applications are found in high volume, high-end consumer products, telecommunication products, defense systems, computers, peripherals, and avionics. Now, due to its economic advantages, smaller companies that cannot afford expensive in-circuit testers are using boundary-scan.