Digital Circuit Design with an Introduction to CPLDs and FPGAs

8.6: Flip Flop Triggering

8.6 Flip Flop Triggering

In Section 8.4 we mentioned that a timing problem exists with the basic JK flip flop. This problem can be eliminated by making the flip flop sensitive to pulse transition. This can be explained best by first defining the transition points of a clock pulse. Figure 8.9 shows a positive pulse and a negative pulse.


Figure 8.9: Positive and negative pulses

A positive pulse is a waveform in which the normal state is logic 0 and changes to logic 1 momentarily to produce a clock pulse. A negative pulse is a waveform in which the normal state is logic 1 and changes to logic 0 momentarily to produce a clock pulse. In either case, the positive edge is the transition from 0 to 1 and the negative edge is the transition from 1 to 0.

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