Digital Principles and Logic Design

5.6: PARITY GENERATOR AND CHECKER

5.6 PARITY GENERATOR AND CHECKER

Parity is a very useful tool in information processing in digital computers to indicate any presence of error in bit information. External noise and loss of signal strength cause loss of data bit information while transporting data from one device to other device, located inside the computer or externally. To indicate any occurrence of error, an extra bit is included with the message according to the total number of 1s in a set of data, which is called parity. If the extra bit is considered 0 if the total number of 1s is even and 1 for odd quantities of 1s in a set of data, then it is called even parity. On the other hand, if the extra bit is 1 for even quantities of 1s and 0 for an odd number of 1s, then it is called odd parity.

5.6.1 Parity Generator

A parity generator is a combination logic system to generate the parity bit at the transmitting side. A table in Figure 5.25 illustrates even parity as well as odd parity for a message consisting of four bits.

Four bit Message

D 3 D 2 D 1 D 0

Even Parity

( P e )

Odd Parity

( P o )

0000

0

1

0001

1

0

0010

1

0

0011

0

1

0100

1

0

0101

0

1

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