TABLE OF CONTENTS Here's what you're going to see in this chapter:
Advantages of a well-prepared floorplan
Floorplan driven by I/O relationships
Floorplan driven by block layout
Floorplan driven by critical nets
Working with all these floorplan drivers at the same time
Efficient block shapes
Leaving enough room in your floorplan
Communication samples regarding floorplanning
Re-using existing layouts for size estimates
Common mistakes people make
Common frustrations and helpful solutions
Floorplanning can be the make-or-break of a chip. A good floorplan could make the chip very easy, very quick to lay out. A bad floorplan can make your life absolutely miserable.
The floorplan is the outline-only design that dictates how all the blocks are going to talk to each other and how the signals will flow between those blocks, as we saw in Chapter 1.
If you just hand the schematic to a team of people who go off, do their little bits of independent work, then come back again 6 weeks later with all their cells done, you are asking for trouble.
When you try to bolt all the individual cells together, you might find that they do not line up. The output of one cell might be on one side of the block, but the cell it's talking to has the input completely on the other side of the block. You can end up with lengthy signals going just everywhere.
You need to...
