This appendix contains full chip individual net plots for:

• Outputs

• Inputs

• Ground

• Substrate contacts

• Powers

• ESD ring

• Well contacts

• Bias

Output Traces

Notice that the source-drain regions for the PMOS devices and the cross-quaded NMOS differential pair are also included, along with the anode and cathode metalization for the ESD diodes.

Figure CS1-94

Simplified Output Traces

This plot shows just the wiring that is associated with the output pads. Notice how the wiring is run symmetrically from the center of each pad to the PMOS devices ensuring even path lengths and identical parasitic capacitances.

Figure CS1-95

Input Traces

This plot shows the symmetry of the amplifier input traces and includes the gate fingers of the input devices. As with the output traces, the inputs are wired symmetrically from the center of the bond pad to ensure balanced trace lengths and identical parasitic capacitance.

Figure CS1-96

Ground Wiring

This plot shows the entire ground wire.

Figure CS1-97

Circuit Ground Wiring

This is a simplified plot of the ground wiring showing only the metal that is used to connect to circuit elements. Notice that the Metal Two wire from bond pad connects in the center of the chip to ensure that the current flowing from each amplifier is evenly distributed.

Figure CS1-98

ESD Ground Wiring

This simplified plot shows the ground wires associated with the ESD protection system. Notice that this wire creates a continuous ring around the active circuitry and that the...