VHDL: Programming By Example, Fourth Edition
No matter what your current level of expertise, nothing will have you writing and verifying concise, efficient VHDL descriptions of hardware designs as fast or as painlessly as this classic tutorial.
TABLE OF CONTENTS VHDL: Programming By Example, Fourth Edition
Chapter 2: Behavioral Modeling
In Chapter 1, we discussed different modeling techniques and touched briefly on behavioral modeling. In this chapter, we discuss behavioral modeling more thoroughly, as well as some of the issues relating to the simulation and synthesis of VHDL models.
Introduction to Behavioral Modeling
The signal assignment statement is the most basic form of behavioral modeling in VHDL. Following is an example:
<b class="bold">a <= b;</b>
This statement is read as follows: a gets the value of b. The effect of this statement is that the current value of signal b is assigned to signal a. This statement is executed whenever signal b changes value. Signal b is in the sensitivity list of this statement. Whenever a signal in the sensitivity list of a signal assignment statement changes value, the signal assignment statement is executed. If the result of the execution is a new value that is different from the current value of the signal, then an event is scheduled for the target signal. If the result of the execution is the same value, then no event is scheduled but a transaction is still generated (transactions are discussed in Chapter 3, Sequential Processing ). A transaction is always generated when a model is evaluated, but only signal value changes cause events to be scheduled.
The next example shows how to introduce a nonzero delay value for the assignment:
<b class="bold">a <= b after 10 ns;</b>
This statement is read as follows: a gets the value...
Copyright The McGraw-Hill Companies, Inc. 2002 under license agreement with Books24x7
