VHDL: Programming By Example, Fourth Edition
No matter what your current level of expertise, nothing will have you writing and verifying concise, efficient VHDL descriptions of hardware designs as fast or as painlessly as this classic tutorial.
TABLE OF CONTENTS VHDL: Programming By Example, Fourth Edition
Chapter 4: Data Types
In this chapter, we examine the object types used in VHDL. The types allowed in VHDL consist of everything from scalar numeric types to composite arrays and records to file types. The first step in looking at the varied VHDL types is to review the VHDL objects that can attain the varied types. Then we use examples to show how many types of descriptions can be made easier to read by using the power of enumerated and composite data types.
Object Types
A VHDL object consists of one of the following:
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Signal, which represents interconnection wires that connect component instantiation ports together.
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Variable, which is used for local storage of temporary data, visible only inside a process.
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Constant, which names specific values.
Signal
Signal objects are used to connect entities together to form models. Signals are the means for communication of dynamic data between entities. A signal declaration looks like this:
<b class="bold">SIGNAL signal_name : signal_type [:= initial_value];</b>
The keyword SIGNAL is followed by one or more signal names. Each signal name creates a new signal. Separating the signal names from the signal type is a colon. The signal type specifies the data type of the information that the signal contains. Finally, the signal can contain an initial value specifier so that the signal value may be initialized.
Signals can be declared in entity declaration sections, architecture declarations, and package declarations. Signals in package declarations are also referred to as global signals because they can be shared among...
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